A Low Power Level Shifter Using Power Gating Technique for Soc Applications

A low-power level shifter (LS) using power gating technique is proposed for logic voltage shifting from near/subthreshold to above-threshold voltage domain. Level shifter allow for effective interfacing between voltage domains supplied by different voltage level. Usually conventional level shifter which can shift any voltage level signal to a desired higher level with low leakage current. The new circuit combines the multi-threshold CMOS technique along with topological modifications to provide a wide voltage conversion range with limited static power , dynamic power and total energy per transition . When implemented in a 45-nm technology process the proposed design converts 250mV input signals to 1V output signal with lesser dynamic power, static power and total energy per consumption while maintaining operational frequencies above 1MHz.